library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity reg_8 is
	port(a		  : in	std_logic_vector (7 downto 0);
		 clk, rst, inc, load : in   std_logic;
		 z	 	  : out	std_logic_vector (7 downto 0)
		 );
end reg_8;

architecture arch_reg_8 of reg_8 is
	signal int_state : std_logic_vector(7 downto 0);
begin
	process (a,int_state,clk,rst, inc, load)
	begin
		if(rst = '1') then
			int_state <= "00000000";
			z <= int_state;
		elsif(clk'event and clk = '1') then
			if (load = '1') then
				int_state <= a;
			elsif (inc = '1') then
				int_state <= int_state + 1;
			end if;			
			z <= int_state;
		end if;
	end process;
end arch_reg_8;